1. Field of the Invention
The present invention relates to a full adder and, more particularly, to a high speed, universal polarity full adder which consumes minimal power and minimal area.
2. Description of the Related Art
Many applications require the use of high speed full adders which are low in power, small in size, and flexible with respect to the polarity (active high/active low) of their input/output signals. FIG. 1 shows the schematic diagram of a prior-art, transistor-based full adder cell 100.
Referring to FIG. 1, it can be seen that full adder cell 100 includes two complex gates and two inverters: a first complex gate 110, a second complex gate 112, a first inverter 114 and a second inverter 116. First complex gate 110, which contains 10 transistors M0–M9, receives a first input signal A, a second input signal B, and a carry input signal CI. In addition, gate 110 also generates a first gate signal FG on node NODE1.
Second complex gate 112, which contains 14 transistors M10–M23, also receives input signal A, input signal B, and carry input signal CI. In addition, gate 112 also receives the first gate signal FG from NODE1, and generates a second gate signal SG on node NODE2.
First inverter 114, which contains two transistors M24/M25, receives the second gate signal SG from NODE2, and generates a sum output signal S. Second inverter 116, which contains two transistors M26/M27, receives the first gate signal FG from NODE1, and generates a carry output signal CO.
In operation, the sum output signal S is high when only input signal A is high, or when only input signal B is high, or when only input signal CI is high, or when input signals A, B and CI are all high.
Referring to FIG. 1, when only input signal A is high, transistors M1, M2, M3, M6 and M7 are turned on, while transistors M0, M4, M5, M8 and M9 are turned off. This forces the first gate signal FG high, driving NODE1 high.
The logic high on NODE1 turns on transistor M17 and turns off transistor M13. Thus transistors M11, M12, M14, M16, M17, M18 and M22 are turned on, while transistors M10, M13, M15, M19, M20, M21 and M23 are turned off. This forces the second gate signal SG low, driving NODE2 low. Transistors M24 and M25 then invert the logic low on NODE2, generating a logic high on the sum output signal S.
Referring to FIG. 1, when only input signal B is high, transistors M0, M3, M4, M8 and M9 are turned on, while transistors M1, M2, M5, M6 and M7 are turned off. This forces the first gate signal FG high, driving NODE1 high.
The logic high on NODE1 turns on transistor M17 and turns off transistor M13. Thus transistors M10, M12, M15, M16, M17, M19 and M23 are turned on, while transistors M11, M13, M14, M18, M20, M21 and M22 are turned off. This forces the second gate signal SG low, driving NODE2 low. Transistors M24 and M25 then invert the logic low on NODE2, generating a logic high on the sum output signal S.
Referring to FIG. 1, when only input signal CI is high, transistors M0, M1, M2, M4 and M5 are turned on, while transistors M3, M6, M7, M8 and M9 are turned off. This forces the first gate signal FG high, driving NODE1 high.
The logic high on NODE1 turns on transistor M17 and turns off transistor M13. Thus transistors M10, M11, M14, M15, M17, M20 and M21 are turned on, while transistors M12, M13, M16, M18, M19, M22 and M23 are turned off. This forces the second gate signal SG low, driving NODE2 low. Transistors M24 and M25 then invert the logic low on NODE2, generating a logic high on the sum output signal S.
Referring to FIG. 1, when input signals A, B and CI are all high, transistors M5–M9 are turned on, while transistors M0–M4 are turned off. This forces the first gate signal FG low, driving NODE1 low.
The logic low on NODE1 turns on transistor M13 and turns off transistor M17. Thus transistors M13, M18, M19, M20, M21, M22 and M23 are turned on, while transistors M10, M11, M12, M14, M15, M16 and M17 are turned off. This forces the second gate signal SG low, driving NODE2 low. Transistors M24 and M25 then invert the logic low on NODE2, generating a logic high on the sum output signal S.
The carry output signal CO is high when only input signals A and B are high, or when only input signals A and CI are high, or when only input signals B and CI are high, or when input signals A, B and CI are all high.
Referring to FIG. 1, when only input signals A and B are high, transistors M3, M6, M7, M8 and M9 are turned on, while transistors M0, M1, M2, M4 and M5 are turned off. This forces the first gate signal FG low, driving NODE1 low. Inverter 116, formed by transistors M26 and M27, then inverts the logic low on NODE1, generating a logic high on the carry output signal CO.
Similarly, when only input signals A and CI are high, transistors M1, M2, M5, M6 and M7 are turned on, while transistors M0, M3, M4, M8 and M9 are turned off. This forces the first gate signal FG low, driving NODE1 low. Inverter 116, formed by transistors M26 and M27, then inverts the logic low on NODE1, generating a logic high on the carry output signal CO.
Furthermore, when only input signals B and CI are high, transistors M0, M4, M5, M8 and M9 are turned on, while transistors M1, M2, M3, M6 and M7 are turned off. This forces the first gate signal FG low, driving NODE1 low. Inverter 116, formed by transistors M26 and M27, then inverts the logic low on NODE1, generating a logic high on the carry output signal CO.
Finally, when input signals A, B and CI are all high, transistors M5–M9 are turned on, while transistors M0–M4 are turned off. This forces the first gate signal FG low, driving NODE1 low. Inverter 116, formed by transistors M26 and M27, then inverts the logic low on NODE1, generating a logic high on the carry output signal CO.
TABLE 1 shows the truth table for a full adder. Referring to TABLE 1, the full adder inputs include input signal A, input signal B and the carry input signal CI. The full adder outputs include sum output signal S and the carry output signal CO. As shown in TABLE 1, sum output signal S and carry output signal CO both depend upon the adder input signals A, B and CI.
Using the data shown in TABLE 1, the Boolean logic equation for the sum output signal S can be easily obtained by constructing a simple Karnaugh map, as shown in TABLE 2 and Eq. 1. Referring to Eq. 1, it can be seen that the sum output signal S will be high only when there are an odd number of ones in the triad {A, B, CI}. Thus, the sum output signal S will be high when only input signal A is high, or when only input signal B is high, or when only input signal CI is high, or when input signals A, B and CI are all high.
Using the data shown in TABLE 1, the Boolean logic equation for the carry output signal CO can be easily obtained by constructing a simple Karnaugh map, as shown in TABLE 3 and Eq. 2. Referring to Eq. 2, it can be seen that the carry output signal CO will be high when at least two of the members in the triad {A, B, CI} are high. Therefore, the carry output signal CO will be high when input signals A and B are high, or when input signals A and CI are high, or when input signals B and CI are high.
TABLE 1InputInputInputOutputOutputABCISCO00000001100101001101100101010111001II111
TABLE 2                     S        =                                            A              _                        ⁢            B            ⁢                                          C                ⁢                l                            _                                +                      A            ⁢                          B              _                        ⁢                                          C                ⁢                l                            _                                +                                    A              _                        ⁢                          B              _                        ⁢            Cl                    +          ABCl                                    Eq        .                                  ⁢        1            
TABLE 3                     CO        =                  AB          +          ACl          +          BCl                                    Eq        .                                  ⁢        2            
The prior-art full adder shown in FIG. 1 suffers from several disadvantages. For example, full adder 100 contains 28 transistors, a very high device count. Furthermore, except for two inverters, the transistors in full adder 100 are stacked up to three high, resulting in large device sizes. The high device count and the high device stacking are serious disadvantages because they increase the total gate capacitance, the total power dissipation and the total cell area.
Another disadvantage of full adder 100 is that its input/output signal polarity cannot be changed without adding inverters at the inputs/outputs of the adder. Thus, for applications which require different input/output signal polarity, the addition of these inverters increases the total gate capacitance, the total power dissipation and the total cell area. Since a full adder has three inputs and two outputs, each of which can be active high or active low, there are 32 different combinations of input/output signal polarity.
From the foregoing discussion, it can be seen that there is a definite need for a high speed full adder which is low in power and small in size. Furthermore, this adder should support all possible combinations of input/output signal polarity, without requiring extra inverters. Additionally, this adder should also provide buffered or unbuffered outputs, in order to drive high/low capacitance loads.